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19-3955; Rev 3; 4/09
27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer
General Description
The MAX9247 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial-data stream. Eighteen bits of video data and 9 bits of control data are encoded and multiplexed onto the serial interface, reducing the serial-data rate. The data-enable input determines when the video or control data is serialized. The MAX9247 pairs with the MAX9248/MAX9250 deserializers to form a complete digital video serial link. Interconnect can be controlled-impedance PCB traces or twisted-pair cable. Proprietary data encoding reduces EMI and provides DC balance. DC balance allows ACcoupling, providing isolation between the transmitting and receiving ends of the interface. The LVDS output is internally terminated with 100. For operating frequencies less than 35MHz, the MAX9247 can also pair with the MAX9218 deserializer. ESD tolerance is specified for ISO 10605 with 10kV Contact Discharge and 30kV Air-Gap Discharge. The MAX9247 operates from a +3.3V core supply and features a separate input supply for interfacing to 1.8V to 3.3V logic levels. This device is available in a 48-lead LQFP package and is specified from -40C to +85C or -40C to +105C.
Features
Preemphasis Improves Eye Diagram and Signal Integrity at the Output Proprietary Data Encoding for DC Balance and Reduced EMI Control Data Sent During Video Blanking Five Control Data Inputs are Single-Bit-Error Tolerant Programmable Phase-Shifted LVDS Signaling Reduces EMI Output Common-Mode Filter Reduces EMI Greater Than 10m STP Cable Drive Wide 2% Reference Clock Tolerance ISO 10605 and IEC 61000-4-2 Level 4 ESD Protection Separate Input Supply Allows Interface to 1.8V to 3.3V Logic +3.3V Core Supply Space-Saving LQFP Package -40C to +85C and -40C to +105C Operating Temperature Ranges
MAX9247
Ordering Information
PART MAX9247ECM+ MAX9247ECM/V+ MAX9247GCM+ MAX9247GCM/V+ TEMP RANGE -40C to +85C -40C to +85C -40C to +105C -40C to +105C PIN-PACKAGE 48 LQFP 48 LQFP 48 LQFP 48 LQFP
Applications
Navigation System Displays In-Vehicle Entertainment Systems Video Cameras LCDs
+Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part.
Pin Configuration
TOP VIEW RGB_IN9 RGB_IN8 RGB_IN7 RGB_IN6 RGB_IN5 RGB_IN4 RGB_IN3 RGB_IN2 RGB_IN1 RGB_IN0 VCC GND
48 47 46 45 44 43 42 41 40 39 38
GND VCCIN RGB_IN10 RGB_IN11 RGB_IN12 RGB_IN13 RGB_IN14 RGB_IN15 RGB_IN16 RGB_IN17 CNTL_IN0 CNTL_IN1
1 2 3 4 5 6 7 8 9 10 11 12
+
37
36 35 34 33 32 31
RNG0 RNG1 VCCLVDS OUT+ OUTLVDSGND LVDSGND CMF PWRDWN VCCPLL PLLGND PRE
MAX9247
30 29 28 27 26 25
13
14
15
16
17
18
19
20
21
22
23
________________________________________________________________ Maxim Integrated Products
GND VCC CNTL_IN2 CNTL_IN3 CNTL_IN4 CNTL_IN5 CNTL_IN6 CNTL_IN7 CNTL_IN8 DE_IN PCLK_IN I.C.
LQFP
24
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer MAX9247
ABSOLUTE MAXIMUM RATINGS
VCC_ to _GND........................................................-0.5V to +4.0V Any Ground to Any Ground...................................-0.5V to +0.5V OUT+, OUT- to LVDSGND ....................................-0.5V to +4.0V OUT+, OUT- Short Circuit to LVDSGND or VCCLVDS .............................................................Continuous OUT+, OUT- Short Through 0.125F (or smaller), 25V Series Capacitor..........................................-0.5V to +16V RGB_IN[17:0], CNTL_IN[8:0], DE_IN, RNG0, RNG1, PRE, PCLK_IN, PWRDWN, CMF to GND......................-0.5V to (VCCIN + 0.5V) Continuous Power Dissipation (TA = +70C) 48-Lead LQFP (derate 21.7mW/C above +70C) ....1739mW ESD Protection Machine Model (RD = 0, CS = 200pF) All Pins to GND ..............................................................200V Human Body Model (RD = 1.5k, CS = 100pF) All Pins to GND ................................................................3kV ISO 10605 (RD = 2k, CS = 330pF) Contact Discharge (OUT+, OUT-) to GND ....................10kV Air-Gap Discharge (OUT+, OUT-) to GND ....................30kV IEC 61000-4-2 (RD = 330, CS = 150pF) Contact Discharge (OUT+, OUT-) to GND ....................10kV Air-Gap Discharge (OUT+, OUT-) to GND ....................15kV Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s)..................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC_ = +3.0V to +3.6V, RL = 100 1%, PWRDWN = high, PRE = low, TA = -40C to +105C, unless otherwise noted. Typical values are at VCC_ = +3.3V, TA = +25C.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS VCCIN = 1.71V to < 3V (Note 3) VCCIN = 3.0V to 3.6V VCCIN = 1.71V to < 3V (Note 3) VCCIN = 3.0V to 3.6V VCCIN = 1.71V to 3.6V, PWRDWN = high or low ICL = -18mA Figure 1 Figure 1 Figure 1 Figure 1 VOUT+ or VOUT- = 0 or 3.6V VOD = 0 VOUT+ = 0, VOUT- = 3.6V VOUT+ = 3.6V, VOUT- = 0 -15 8 5.5 1.125 1.29 250 335 VIN = -0.3V to 0 (MAX9247ECM), VIN = -0.15V to 0 (MAX9247GCM) VIN = 0 to (VCCIN + 0.3V) MIN 0.65 x VCCIN 2 -0.3 -0.3 TYP MAX VCCIN + 0.3 0.3 + VCCIN 0.3 x VCCIN +0.8 UNITS
SINGLE-ENDED INPUTS (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, PCLK_IN, PWRDWN, RNG_, PRE) High-Level Input Voltage Low-Level Input Voltage VIH VIL V V
Input Current
IIN
-100
+20
A
-20
+20 -1.5 450 20 1.475 20 +15 15 V mV mV V mV mA mA
Input Clamp Voltage LVDS OUTPUTS (OUT+, OUT-) Differential Output Voltage Change in VOD Between Complementary Output States Common-Mode Voltage Change in VOS Between Complementary Output States Output Short-Circuit Current Magnitude of Differential Output Short-Circuit Current Output High-Impedance Current
VCL VOD VOD VOS VOS IOS IOSD
IOZ
PWRDWN = low or VCC_ = 0
-1
+1
A
2
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27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC_ = +3.0V to +3.6V, RL = 100 1%, PWRDWN = high, PRE = low, TA = -40C to +105C, unless otherwise noted. Typical values are at VCC_ = +3.3V, TA = +25C.) (Notes 1, 2)
PARAMETER Differential Output Resistance SYMBOL RO 2.5MHz 5MHz RL = 100 1%, CL = 5pF, continuous 10 transition words 10MHz 20MHz 35MHz 42MHz Power-Down Supply Current ICCZ (Note 4) PRE = 0 PRE = 1 PRE = 0 PRE = 1 PRE = 0 PRE = 1 PRE = 0 PRE = 1 PRE = 0 PRE = 1 PRE = 0 PRE = 1 60 50 33 23 18 CONDITIONS MIN 78 TYP 110 15 MAX 147 25 27 25 27 28 30 39 42 65 69 70 75 50 A mA UNITS
MAX9247
Worst-Case Supply Current
ICCW
AC ELECTRICAL CHARACTERISTICS
(VCC_ = +3.0V to +3.6V, RL = 100 1%, CL = 5pF, PWRDWN = high, PRE = low, TA = -40C to +105C, unless otherwise noted. Typical values are at VCC_ = +3.3V, TA = +25C.) (Note 3)
PARAMETER PCLK_IN TIMING REQUIREMENTS Clock Period Clock Frequency Clock Frequency Difference from Deserializer Reference Clock Clock Duty Cycle Clock Transition Time SWITCHING CHARACTERISTICS Output Rise Time Output Fall Time Input Setup Time Input Hold Time tRISE tFALL tSET tHOLD 20% to 80%, VOD 250mV, Figure 3 80% to 20%, VOD 250mV, Figure 3 Figure 4 Figure 4 PRE = low PRE = high PRE = low PRE = high 3 3 280 240 280 240 370 320 370 320 ps ps ns ns tT fCLK fCLK DC tR, tF tHIGH/tT or tLOW/tT, Figure 2 Figure 2 Figure 2 MAX9247ECM MAX9247GCM MAX9247ECM MAX9247GCM 23.8 28.6 2.5 2.5 -2 35 50 400.0 400.0 42.0 35.0 +2 65 2.5 ns MHz % % ns SYMBOL CONDITIONS MIN TYP MAX UNITS
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27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer MAX9247
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC_ = +3.0V to +3.6V, RL = 1001%, CL = 5pF, PWRDWN = high, PRE = low, TA = -40C to +105C, unless otherwise noted. Typical values are at VCC_ = +3.3V, TA = +25C.) (Note 3)
PARAMETER Serializer Delay PLL Lock Time Power-Down Delay Peak-to-Peak Output Jitter SYMBOL tSD tLOCK tPD tJITT Figure 5 Figure 6 Figure 7 Measured with PRBS input pattern at 840Mbps data rate 840Mbps data rate, CMF open, Figure 8 840Mbps data rate, CMF 0.1F to ground, Figure 8 22 12 CONDITIONS MIN 3.10 x tT + 2.0 TYP MAX 3.10 x tT + 8.0 17,100 x tT 1 150 70 mV 50 UNITS ns ns s ps
Peak-to-Peak Output Offset Voltage
VOS(P-P)
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground, except VOD, VOD, and VOS. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25C. Note 3: Parameters are guaranteed by design and characterization and are not production tested. Limits are set at 6 sigma. Note 4: All LVTTL/LVCMOS inputs, except PWRDWN at 0.3V or VCCIN - 0.3V. PWRDWN is 0.3V.
4
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27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer
Typical Operating Characteristics
(VCC_ = +3.3V, RL = 100, TA = +25C, unless otherwise noted.)
WORST-CASE PATTERN SUPPLY CURRENT vs. FREQUENCY
MAX9247 toc01
MAX9247
EYE DIAGRAM WITHOUT PREEMPHASIS
MAX9247 toc02
EYE DIAGRAM WITH PREEMPHASIS
PRE = HIGH REFCLK = 42MHz 2 METER CAT5 CABLE 100 TERMINATION GND
MAX9247 toc03
70 60 SUPPLY CURRENT (mA) 50 40 WITH PREEMPHASIS
PRE = LOW REFCLK = 42MHz
2 METER CAT5 CABLE 100 TERMINATION
100mV/div 30 20 10 0 0 10 20 30 40 200ps/div WITHOUT PREEMPHASIS GND
100mV/div
200ps/div
FREQUENCY (MHz)
BIT-ERROR RATE vs. CABLE LENGTH
CAT5 CABLE
MAX9247 toc04
CABLE LENGTH vs. FREQUENCY BIT-ERROR RATE < 10-9
40 35 FREQUENCY (MHz) 30 25 20 15 10 5 0 2 4 6 8 10 12 14 16 18 20
MAX9247 toc05
1.00E-14
45
1.00E-13 BIT-ERROR RATE
1.00E-12
1.00E-11
REFCLK = 42MHz 840Mbps DATA RATE FOR CABLE LENGTH < 10m BER < 10-12 0 2 4 6 8 10 12
1.00E-10 CAT5 CABLE LENGTH (m)
CABLE LENGTH (m)
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27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer MAX9247
Pin Description
PIN 1, 13, 37 2 NAME GND VCCIN RGB_IN10- RGB_IN17, RGB_IN0- RGB_IN9 CNTL_IN0, CNTL_IN1, CNTL_IN2- CNTL_IN8 VCC FUNCTION Input Buffer Supply and Digital Supply Ground Input Buffer Supply Voltage. Bypass to GND with 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to GND.
3-10, 39-48
11, 12, 15-21
LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN when DE_IN is low. Internally pulled down to GND. Digital Supply Voltage. Bypass to GND with 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. LVTTL/LVCMOS Data-Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally pulled down to GND. LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL reference clock. Internally pulled down to GND. Internally Connected. Leave unconnected for normal operation. Preemphasis Enable Input. Drive PRE high to enable preemphasis. PLL Supply Ground PLL Supply Voltage. Bypass to PLLGND with 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. Common-Mode Filter. Optionally connect a capacitor between CMF and ground to filter commonmode switching noise. LVDS Supply Ground Inverting LVDS Serial-Data Output Noninverting LVDS Serial-Data Output LVDS Supply Voltage. Bypass to LVDSGND with 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the PCLK_IN frequency as shown in Table 3. Internally pulled down to GND. LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
14, 38
22
DE_IN
23 24 25 26 27 28 29 30, 31 32 33 34 35 36
PCLK_IN I.C. PRE PLLGND VCCPLL PWRDWN CMF LVDSGND OUTOUT+ VCCLVDS RNG1 RNG0
6
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27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer
Functional Diagram
MAX9247
PRE RGB_IN CNTL_IN DE_IN 1 INPUT LATCH 0 DC BALANCE/ ENCODE OUT+ PAR-TO-SER OUTCMF
PCLK_IN RNG0 RNG1
PLL
TIMING AND CONTROL
PWRDWN
MAX9247
OUT+
RL/2
VOD OUTRL/2 GND ((OUT+) + (OUT-))/2 OUTVOS(-) OUT+ VOS = |VOS(+) - VOS(-)| VOS(+) VOS(-) VOS
VOD(+) VOD = 0V VOD(-) (OUT+) - (OUT-) VOD = |VOD(+) - VOD(-)| VOD(-)
Figure 1. LVDS DC Output Load and Parameters
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7
27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer MAX9247
tT
VIHmin PCLK_IN tHIGH VILmax tF tR tLOW
Figure 2. Parallel Clock Requirements
OUT+ RL OUTCL CL
80%
80%
20% (OUT+) - (OUT-) tRISE tFALL
20%
Figure 3. Output Rise and Fall Times
PCLK_IN VILmax
VIHmin
tSET RGB_IN[17:0] VIHmin CNTL_IN[8:0] VILmax DE_IN
tHOLD
VIHmin VILmax
Figure 4. Synchronous Input Timing
8
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27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer MAX9247
EXPANDED TIME SCALE
RGB_IN CNTL_IN
N
N+1
N+2
N+3
N+4
PCLK_IN
N-1 OUT_
N
tSD
BIT 0
BIT 19
Figure 5. Serializer Delay
PWRDWN
VILmax tLOCK
(OUT+) - (OUT-)
HIGH IMPEDANCE
VOD = 0V
PCLK_IN
Figure 6. PLL Lock Time
PWRDWN VILmax tPD (OUT+) - (OUT-) HIGH IMPEDANCE
PCLK_IN
Figure 7. Power-Down Delay
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27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer MAX9247
OUT-
OUT+
((OUT+) + (OUT-))/2
VOS(P-P)
VOS(P-P)
Figure 8. Peak-to-Peak Output Offset Voltage
Detailed Description
The MAX9247 DC-balanced serializer operates at a 2.5MHz-to-42MHz parallel clock frequency, serializing 18 bits of parallel video data RGB_IN[17:0] when the data-enable input DE_IN is high, or 9 bits of parallel control data CNTL_IN[8:0] when DE_IN is low. The RGB video input data are encoded using 2 overhead bits, EN0 and EN1, resulting in a serial word length of 20 bits (see Table 1). Control inputs are mapped to 19 bits and encoded with 1 overhead bit, EN0, also resulting in a 20-bit serial word. Encoding reduces EMI and
maintains DC balance across the serial cable. Two transition words, which contain a unique bit sequence, are inserted at the transition boundaries of video-tocontrol and control-to-video phases. Control data inputs C0 to C4 are mapped to 3 bits each in the serial control word (see Table 2). At the deserializer, 2 or 3 bits at the same state determine the state of the recovered bit, providing single-bit-error tolerance for C0 to C4. Control data that may be visible if an error occurs, such as VSYNC and HSYNC, can be connected to these inputs. Control data inputs C5 to C8 are mapped to 1 bit each.
Table 1. Serial Video Phase Word Format
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S13 16 S14 17 S15 18 S16 19 S17 EN0 EN1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 Bit 0 is the LSB and is serialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.
Table 2. Serial Control Phase Word Format
0 1 2 3 4 5 6 7 8 9 10 11 C3 12 C3 13 C4 14 C4 15 C4 16 C5 17 C6 18 C7 19 C8 EN0 C0 C0 C0 C1 C1 C1 C2 C2 C2 C3 Bit 0 is the LSB and is serialized first. C[8:0] are the control inputs.
10
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27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer MAX9247
CONTROL PHASE TRANSITION PHASE VIDEO PHASE TRANSITION PHASE CONTROL PHASE
PCLK_IN
CNTL_IN
DE_IN
RGB_IN
= NOT SAMPLED BY PCLK_IN
Figure 9. Transition Timing
Transition Timing
The transition words require interconnect bandwidth and displace control data. Therefore, control data is not sampled (see Figure 9): * Two clock cycles before DE_IN goes high * During the video phase * Two clock cycles after DE_IN goes low The last sampled control data are latched at the deserializer control data outputs during the transition and video phases. Video data are latched at the deserializer RGB data outputs during the transition and control phases.
13 show the AC-coupled serializer and deserializer with four capacitors per link.
Selection of AC-Coupling Capacitors
See Figure 14 for calculating the capacitor values for AC-coupling depending on the parallel clock frequency. The plot shows capacitor values for two- and fourcapacitor-per-link systems. For applications using less than 18MHz clock frequency, use 0.1F capacitors.
Frequency-Range Setting RNG[1:0]
The RNG[1:0] inputs select the operating frequency range of the MAX9247 serializer. An external clock within this range is required for operation. Table 3 shows the selectable frequency ranges and corresponding data rates for the MAX9247.
Applications Information
AC-Coupling Benefits
AC-coupling increases the common-mode voltage to the voltage rating of the capacitor. Two capacitors are sufficient for isolation, but four capacitors--two at the serializer output and two at the deserializer input--provide protection if either end of the cable is shorted to a high voltage. AC-coupling blocks low-frequency ground shifts and common-mode noise. The MAX9247 serializer can also be DC-coupled to the MAX9248/ MAX9250 deserializers. Figures 10 and 12 show an AC-coupled serializer and deserializer with two capacitors per link. Figures 11 and
Table 3. Parallel Clock Frequency Range Select
RNG1 0 0 1 1 RNG0 0 1 0 1 PARALLEL CLOCK (MHz) 2.5 to 5 5 to10 10 to 20 20 to 42 SERIAL-DATA RATE (Mbps) 50 to 100 100 to 200 200 to 400 400 to 840
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11
27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer MAX9247
VCC 130 * PAR-TO-SER OUT * 82 82 IN 130 DC BALANCE/ DECODE SER-TO-PAR 1 0
PRE RGB_IN CNTL_IN DE_IN 1 0 DC BALANCE/ ENCODE INPUT LATCH
R/F OUTEN RGB_OUT CNTL_OUT DE_OUT
CMF
RNG0 PCLK_IN RNG0 RNG1 PWRDWN PLL TIMING AND CONTROL RNG1
PCLK_OUT PLL REF_IN TIMING AND CONTROL PWRDWN LOCK
MAX9247
MAX9250
CERAMIC RF SURFACE-MOUNT CAPACITOR *CAPACITORS CAN BE AT EITHER END.
100 DIFFERENTIAL STP CABLE
Figure 10. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Two Capacitors per Link
VCC 130 130 DC BALANCE/ DECODE SER-TO-PAR 1 0
PRE DC BALANCE/ ENCODE INPUT LATCH RGB_IN CNTL_IN DE_IN 1 0 PAR-TO-SER
R/F OUTEN RGB_OUT CNTL_OUT DE_OUT
OUT 82 82
IN
CMF
RNG0 PCLK_IN RNG0 RNG1 PWRDWN PLL TIMING AND CONTROL RNG1
PCLK_OUT PLL REF_IN TIMING AND CONTROL PWRDWN LOCK
MAX9247
MAX9250
CERAMIC RF SURFACE-MOUNT CAPACITOR
100 DIFFERENTIAL STP CABLE
Figure 11. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Four Capacitors per Link
12
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27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer MAX9247
VCC 130 * PAR-TO-SER OUT * 82 130 DC BALANCE/ DECODE SER-TO-PAR IN+ IN82 1 FIFO 0
PRE RGB_IN CNTL_IN DE_IN DC BALANCE/ ENCODE INPUT LATCH 1 0
R/F RGB_OUT CNTL_OUT DE_OUT PCLK_OUT
CMF
PCLK_IN RNG0 RNG1 PWRDWN
REFCLK PLL TIMING AND CONTROL
PLL SSPLL TIMING AND CONTROL SS PWRDWN LOCK
MAX9247
RNG[0:1] CERAMIC RF SURFACE-MOUNT CAPACITOR *CAPACITORS CAN BE AT EITHER END. 100 DIFFERENTIAL STP CABLE
MAX9248
Figure 12. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Two Capacitors per Link
VCC 130 130 DC BALANCE/ DECODE SER-TO-PAR IN+ OUT IN82 82 1 FIFO 0
PRE DC BALANCE/ ENCODE INPUT LATCH RGB_IN CNTL_IN DE_IN PAR-TO-SER 1 0
R/F RGB_OUT CNTL_OUT DE_OUT PCLK_OUT
CMF
PCLK_IN RNG0 RNG1 PWRDWN
REFCLK PLL TIMING AND CONTROL
PLL SSPLL TIMING AND CONTROL SS PWRDWN LOCK
MAX9247
RNG[0:1] CERAMIC RF SURFACE-MOUNT CAPACITOR 100 DIFFERENTIAL STP CABLE
MAX9248
Figure 13. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Four Capacitors per Link
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13
27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer MAX9247
LVDS Output Preemphasis (PRE)
AC-COUPLING CAPACITOR VALUE vs. PARALLEL CLOCK FREQUENCY
140 120 CAPACITOR VALUE (nF) 100 80 60 40 20 TWO CAPACITORS PER LINK 0 18 21 24 27 30 33 36 39 42 PARALLEL CLOCK FREQUENCY (MHz) FOUR CAPACITORS PER LINK
The MAX9247 features a preemphasis mode where extra current is added to the output and causes the amplitude to increase by 40% to 50% at the transition point. Preemphasis helps to get a faster transition, better eye diagram, and improve signal integrity. See the Typical Operating Characteristics. The additional current is turned on for a short time (360ps, typ) during data transition, and then turned off. Enable preemphasis by driving PRE high.
Power-Down and Power-Off
Driving PWRDWN low stops the PLL, switches out the integrated 100 output termination, and puts the output in high impedance to ground and differential. With PWRDWN 0.3V and all LVTTL/LVCMOS inputs 0.3V or VCCIN - 0.3V, supply current is reduced to 50A or less. Driving PWRDWN high starts PLL lock to PCLK_IN and switches in the 100 output termination resistor. The LVDS output is not driven until the PLL locks. The LVDS output is high impedance to ground and 100 differential. The 100 integrated termination pulls OUT+ and OUT- together while the PLL is locking so that VOD = 0V. If VCC = 0, the output resistor is switched out and the LVDS outputs are high impedance to ground and differential.
Figure 14. AC-Coupling Capacitor Values vs. Clock Frequency of 18MHz to 42MHz
Termination
The MAX9247 has an integrated 100 output-termination resistor. This resistor damps reflections from induced noise and mismatches between the transmission line impedance and termination resistors at the deserializer input. With PWRDWN = low or with the supply off, the output termination is switched out and the LVDS output is high impedance.
PLL Lock Time
The PLL lock time is set by an internal counter. The lock time is 17,100 PCLK_IN cycles. Power and clock should be stable to meet the lock-time specification.
Common-Mode Filter
The integrated 100 output termination is made up of two 50 resistors in series. The junction of the resistors is connected to the CMF pin for connecting an optional common-mode filter capacitor. Connect the filter capacitor to ground close to the MAX9247 as shown in Figure 15. The capacitor shunts common-mode switching current to ground to reduce EMI.
Input Buffer Supply
The single-ended inputs (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, RNG0, RNG1, PRE, PCLK_IN, and PWRDWN) are powered from VCCIN. VCCIN can be connected to a 1.71V to 3.6V supply, allowing logic inputs with a nominal swing of VCCIN. If no power is applied to VCCIN when power is applied to VCC, the inputs are disabled and PWRDWN is internally driven low, putting the device in the power-down state.
OUT+ RO/2 CMF RO/2 OUTCCMF
Power-Supply Sequencing of MAX9247 and MAX9248/MAX9250 Video Link
The MAX9247 and MAX9248/MAX9250 video link can be powered up in several ways. The best approach is to keep both MAX9247 and MAX9248 powered down while supplies are ramping up and PCLK_IN of the MAX9247 and REFCLK of the MAX9248/MAX9250 are stabilizing. After all of the power supplies of the MAX9247 and MAX9248/MAX9250 are stable, including PCLK_IN and REFCLK, do the following: 1) Power up the MAX9247 first
Figure 15. Common-Mode Filter Capacitor Connection
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27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer
2) Wait for at least tLOCK of MAX9247 (or 17100 x tT) to get activity on the link 3) Power up the MAX9248 Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
MAX9247
Power-Supply Circuits and Bypassing
The MAX9247 has isolated on-chip power domains. The digital core supply (VCC) and single-ended input supply (VCCIN) are isolated but have a common ground (GND). The PLL has separate power and ground (VCCPLL and PLLGND) and the LVDS input also has separate power and ground (VCCLVDS and LVDSGND). The grounds are isolated by diode connections. Bypass each VCC, VCCIN, VCCPLL, and VCCLVDS pin with high-frequency, surfacemount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin.
Board Layout
Separate the LVTTL/LVCMOS inputs and LVDS output to prevent crosstalk. A four-layer PCB with separate layers for power, ground, and signals is recommended.
ESD Protection
The MAX9247 ESD tolerance is rated for IEC 61000-42, Human Body Model, Machine Model, and ISO 10605 standards. IEC 61000-4-2 and ISO 10605 specify ESD tolerance for electronic systems. The IEC 61000-4-2 discharge components are C S = 150pF and R D = 330 (Figure 16). For IEC 61000-4-2, the LVDS outputs are rated for 8kV Contact Discharge and 15kV AirGap Discharge. The Human Body Model discharge components are CS = 100pF and RD = 1.5k (Figure 17). For the Human Body Model, all pins are rated for 3kV Contact Discharge. The ISO 10605 discharge components are CS = 330pF and RD = 2k (Figure 18). For ISO 10605, the LVDS outputs are rated for 10kV contact and 30kV air discharge. The Machine Model discharge components are C S = 200pF and RD = 0 (Figure 19).
RD 2k CHARGE-CURRENTLIMIT RESISTOR DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
LVDS Output
The LVDS output is a current source. The voltage swing is proportional to the termination resistance. The output is rated for a differential load of 100 1%.
Cables and Connectors
Interconnect for LVDS typically has a differential impedance of 100. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities.
RD 330 CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 150pF DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
HIGHVOLTAGE DC SOURCE
CS 330pF
Figure 16. IEC 61000-4-2 Contact Discharge ESD Test Circuit
RD 1.5k DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
Figure 18. ISO 10605 Contact Discharge ESD Test Circuit
RD 0 CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 200pF DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF
Figure 17. Human Body ESD Test Circuit
Figure 19. Machine Model ESD Test Circuit
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27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer MAX9247
Chip Information
PROCESS: CMOS
PACKAGE TYPE 48 LQFP
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE CODE C48+5 DOCUMENT NO. 21-0054
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27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer
Revision History
REVISION NUMBER 2 3 REVISION DATE 5/08 4/09 DESCRIPTION Corrected LQFP package, added +105C part, changed temperature limits for +105C rated part, and added Machine Model ESD text and diagram Added /V parts in the Ordering Information table and added new PowerSupply Sequencing of MAX9247 and MAX9248/MAX9250 Video Link section PAGES CHANGED 1-6, 15-19 1, 14
MAX9247
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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